A continuing need exists for lower power, less expensive, and physically smaller wireless devices to meet existing and future demands of portable and other electronic communications. Such demands are particularly prominent in cellular telephone, paging, wireless modem, and other applications. Traditionally, receivers have used a superheterodyne architecture that achieves acceptable results but requires a mixture of on-chip components with an excessive number of off-chip components. The use of off-chip components is particularly undesirable for several reasons since off-chip components make such architectures larger, consume more power, less likely to maintain precise tuning, and more expensive than desired. In an attempt to address these concerns, direct conversion and low-IF receiver architectures have become more popular, with more and more electronic functions being performed on-chip.
One particularly challenging receiver component to integrate on-chip with other components has been the IF filter. The IF filter is typically a bandpass filter which resides downstream of an RF downconversion mixer and upstream of demodulation and baseband processing. Conventionally, local oscillators which drive downconversion mixers are designed and/or tuned so that the downconversion mixer generates a constant, fixed IF frequency regardless of the RF frequency channel being received. Often the IF filter is a bulky component or collection of components that exhibit this same constant, fixed center frequency and are located off-chip. One of the tasks a receiver designer must then perform is to select sufficiently accurate components or otherwise tune components so that the IF filter precisely exhibits a center frequency equal to the fixed IF frequency. If an IF filter exhibits a center frequency that does not closely match the fixed IF frequency, then signal-to-noise decrease and other signal deterioration effects result.
When the IF filter is implemented on-chip using conventional semiconductor formation processes, the resulting resistors, capacitors, and other analog component values often exhibit large variations over temperature, within a single die and wafer, and between different semiconductor batches. Actual resistive and/or capacitive values twenty percent greater than or less than their nominal values are not unusual. In many receiver applications, this variation in component values leads to an unacceptably imprecise IF filter center frequency, which exhibits too much variation over temperature and between different semiconductor dice, wafers, and batches.
Of course, conventional semiconductor processing techniques can also form passive analog components with lower tolerance values, but the consequences of achieving the lower tolerance values may themselves be undesirable. For example, a resistor having a given nominal resistance value may be implemented in a larger die area with greater precision by using relatively high doping, or in a smaller die area with less precision by using relatively low doping. However, the use of a greater die area to obtain a greater precision is undesirable because it leads to a more expensive product and otherwise consumes precious die area that may be better used for other functions.
Some conventional receivers address the imprecise on-chip IF filter center frequency problem by designing tunable IF filters. Unfortunately, the implementation of an on-chip tunable IF filter is itself undesirable. For example, a switched-capacitor filter design may be capable of achieving sufficient center frequency precision, but the high speed clock and switching noise which characterize this filter design make it unsuitable for many receiver applications. Continuous time filtering (e.g., gm-C filters) may also be capable of achieving sufficient center frequency precision, but the needed precision requires complex filter-tuning circuitry which increases power consumption and uses precious semiconductor die area that can be better used for other functions.